In the semiconductor manufacturing process, a deep trench has been widely used in devices, such as when manufacturing a capacitor of a dynamic random access memory (DRAM) unit. FIG. 1 includes steps of manufacturing the deep trenches applied to a capacitor of a DRAM unit. In FIG. 1(a), a dielectric layer 11 is formed on a silicon substrate 10 and is usually made of silicon dioxide/silicon nitride/silicon dioxide or just silicon dioxide. This dielectric layer is used as a hard mask for a subsequent etching process. The dielectric layer 11 is patterned by a photolithography and an etching process. In FIG. 1(b), a photoresist layer 12 is formed on the dielectric layer 11 and a pattern is defined on photoresist layer 12 by a photolithography process. A window of hard mask 13 on the dielectric layer 11 is formed by a dry anisotropic etching process, then the pattern is transferred to the silicon substrate 10 after removing the photoresist layer 12 as shown in FIG. 1(c). Thereafter, the part of the silicon substrate 10 which is not covered by the hard mask is etched by another dry etching process to obtain a deep trench as shown in FIGS. 1(d) and 1(e).
However, an oxide-rich-polymer 14 will remain at the sidewalls and the bottom of the trenches during the dry etching process. In order to remove this polymer, a wet etching process is commonly used. A buffer oxide etcher (BOE) containing a mixture of hydrofluoric acid and ammonium fluoride is used as an etching agent for the wet etching process. However, the polymer deposition may be changed due to the poor quality of the BOE buffer, the changed chamber condition of the dry etching process, the performance of the spin dryer in the wet etching machine, or a reduced size of the deep trench, resulting in that the BOE solution can not enter the bottom of the deep trench easily. Therefore, the polymer in the bottom of the deep trench can not be removed completely by the wet etching process.
After cleaning the deep trench, another dielectric layer is formed on the silicon substrate and then the trenches are filled with polysilicon or .alpha.-silicon, as shown in FIG. 2. If the polymer in the trench is not removed completely, it will influence the quality of the dielectric layer so that the capacitance of the cell will be reduced or a current leakage will occur. Furthermore, the polysilicon or .alpha.-silicon will not fill the trench very well resulting in an occurrence of a void or a seam on the sidewall, poor quality of DRAM, or even a decreased yield of DRAM.
Because the size of the semiconductor device will be minimized, the hole size of the trench of a capacitor in a DRAM unit becomes smaller, the ratio of hole size (0.35 .mu.m) to depth (7 .mu.m) is 1:20 generally, and it becomes harder to clean the polymer in such a small hole of the trench by a wet etching process. For the above reasons, it is desirable to develop a method to improve the defects of the prior art. It is attempted by the applicant to develop such a process.